As VLSI process technology advances, the noise problem is becoming a major issue for chip designers. If two nets are physically adjacent, one net may introduce a glitch noise to another when one is switching and the other is quiet, or a delay noise when the two nets transit at the same time in specific directions (for example, in the same direction for speedup and opposite directions for slowdown). The net affected by the noise is referred to as a victim, whereas the neighboring nets which affect it are referred to as aggressors. A crosstalk noise may cause functional failure if its induced glitch noise is incorrectly latched, or delay faults if its induced delay noise incurs timing violations.
Timing correlations between transitions in aggressor and victim nets are usually captured by switching windows obtained by static timing analysis (STA). A switching window is a time interval in which a net can make transitions. If the switching windows of an aggressor and a victim do not overlap, the aggressor cannot induce delay noise. If the switching windows of two aggressor nets do not overlap, this combination of aggressors cannot simultaneously contribute to a noise fault. Pruning by switching windows is extremely efficient because STA is of linear complexity with respect to the size of a circuit.
The simplicity of pruning heuristics comes at a cost. STA does not take into account the functional correlations between signals. Therefore the results of noise analysis based on the layout information and switching windows might be overly pessimistic. Moreover, the conventional procedures simply propagate all noises on each net to the path's end. Because of the temporal and functional correlations among the signals along a path, the probability that worst-case noises would all be summed up is generally very slight.
Prior work on using circuit functionality to reduce the pessimism in noise analysis has taken on different flavors. One conventional method observes that some signals may always transit in opposite directions, and uses such functional correlation to estimate noise delay faults in critical paths. Another exploits compatible output don't care sets to prune transitions at aggressors, leaving only those that attack victims at their care state. Another uses logic implications between nets to specify feasible switching behaviors, and form a constraint graph from which noise is estimated by finding a maximum weighted independent set of aggressors. Another conventional approach introduces a Boolean satisfiability (SAT) formulation to the noise analysis problem, which reduces the analysis to the search for two input patterns which could be successively applied to a circuit to justify the feasibility of simultaneous transitions at a chosen subset of aggressors.
However, in spite of these conventional attempts to incorporate functional correlations into noise analysis, a general and practically viable solution to this problem is still lacking in the conventional methods, because they impose over-simplified assumptions about the delay models (like fixed delays) or about the captured functional correlations.